Summer Sale Limited Time 65% Discount Offer - Ends in 0d 00h 00m 00s - Coupon code: ecus65

ARM EN0-001 - ARM Accredited Engineer

ARM EN0-001 Premium Access     Download Demo    
Page: 6 / 7
Total 210 questions

In the VFPv4-D32 architecture, which of the following best describes the arrangement of the registers?

A.

D0..D31 and S0..S31 are separate register banks

B.

D0..D31 overlap with S0..S63

C.

D0..D15 overlap with S0..S31, and D16..D31 do not overlap with any single-precision registers

D.

D0 overlaps with S0, D1 with S1 etc. up to D31 and S31

The Q-flag in the program status register (PSR) indicates which of the following?

A.

Arithmetic overflow has occurred

B.

Processor is in Thumb execution state

C.

Imprecise data aborts are currently disabled

D.

Saturation has occurred after execution of a saturated arithmetic instruction

Using a Generic Interrupt Controller (GIC), when the interrupt handler writes to the End of Interrupt Register (ICCEOIR), which of the following state transitions might occur for that interrupt ID?

A.

Inactive to Active

B.

Pending to Active

C.

Active to Inactive

D.

Active to Pending

How many ARM core registers and PSRs (Program Status Registers) are available to the programmer in User mode on a Cortex-A9?

A.

16

B.

17

C.

18

D.

32

Many ARM cores provide two instruction sets, ARM and Thumb. Which THREE of the following statements apply to the Thumb instruction set implemented for the ARMv7-A architecture? (Choose three)

A.

Thumb is a hybrid 16/32-bit instruction set

B.

No Thumb instructions can be conditionally executed

C.

Thumb code is always slower than the equivalent ARM code

D.

Some routines take more instructions in Thumb code than in the equivalent ARM code

E.

The Thumb instruction set can access the Advanced SIMD "NEON" instructions

F.

Thumb code is always more power-efficient than equivalent ARM code

Which one of the following features must any processor support to conform to the ARMv7-A architecture?

A.

NEON (Advanced SIMD)

B.

Thumb-2 technology

C.

TrustZone (Security Extensions)

D.

Generic Interrupt Controller

Which of the following would enable the use of a symmetric multiprocessing (SMP) operating system?

A.

A dual-core Cortex-A9 processor

B.

A Cortex-R4 processor with a Cortex-M3 system controller

C.

A Cortex-A8 processor with a graphics processing unit (GPU)

D.

A uni-core Cortex-A5 processor with a digital signal processor (DSP)

Which instruction would be used to return from a Reset exception?

A.

MOVS PC, R14

B.

MOVSPC, R13

C.

Architecturally not defined

D.

SUBS PC, R14, #4

In which of the following situations would you use a mutex to avoid synchronization problems?

A.

A single-threaded application needs to manage two separate UART peripherals

B.

Two independent threads running on a single processor both need to access a single UART

C.

In a dual-core system, a UART is accessed by a single thread running on one of the processors

D.

In a dual-core system, processor A needs to access UART A and processor B needs to access UART B

When a linker is removing unused sections during a static link (for example, -remove or -gc-sections), it finds the sections to keep by following all relocations starting from:

A.

The entry point(s).

B.

The function named 'main'.

C.

All local functions and variables.

D.

The reset vector.