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ARM EN0-001 - ARM Accredited Engineer

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Total 210 questions

In an ARMv7-R processor, with which level of the memory system is the Memory Protection Unit (MPU) associated?

A.

Level 1

B.

Level 2

C.

Level 3

D.

Level 4

Processors which implement the ARMv7-A architecture can be configured to allow unaligned memory access. Unaligned accesses have a number of advantages, disadvantages, and limitations.

Which TWO of the following statements are true? (Choose two)

A.

Unaligned accesses may take more cycles to execute than aligned accesses

B.

Unaligned loads and stores are necessary for accessing fields in packed structures

C.

A program compiled using unaligned accesses can be safely executed on all ARMv7-A devices

D.

If the relevant control register setting is enabled all loads and stores can function from unaligned addresses

E.

Unaligned accesses can only be made to Normal memory

In the Generic Interrupt Controller (GIC) architecture, which of the following ID numbers are reserved for interrupts that are private to a CPU interface?

A.

ID0-ID7

B.

ID0-ID15

C.

ID0-ID31

D.

ID0-ID63

Using a lower optimization level when compiling will:

A.

Produce faster code.

B.

Produce smaller code.

C.

Produce non standard-compliant code.

D.

Produce code that might be easier to debug.

Which of these items is typically shared between threads running in the same Operating System (OS) process?

A.

Stack

B.

Memory map

C.

Register values

D.

Program Counter

In which of the following scenarios would cache maintenance operations be necessary in an ARMv7 system?

A.

Before executing code that uses the NEON instruction set

B.

Before handling an interrupt request raised by an external device

C.

Before checking the status of a semaphore

D.

Before reading cacheable memory that has been written to by an external bus master

What is the value of R2 after execution of the following instruction sequence?

MOV R3, #0xBA

MOV R2/#0x10

BIC R2, R3, R2

A.

R2 = 0xBB

B.

R2 = 0xCB

C.

R2 = 0xAA

D.

R2 = 0xCC

Clicking the Start button in a debugger:

A.

Begins processor execution.

B.

Resets the processors.

C.

Erases existing breakpoints.

D.

Puts the processor(s) into debug state.

An advantage of native compiling over cross compiling is that:

A.

It can enable the final code to be smaller, and execute more quickly.

B.

It allows greater parallelism when building code by utilizing many processors.

C.

The compiler is able to produce error and warning messages in a range of languages.

D.

Build scripts can detect details of the target, and automatically configure the build to match.

Which of the following ARM processors has a superscalar micro architecture?

A.

ARM926EJ-S

B.

Cortex-M0

C.

Cortex-M3

D.

Cortex-A8