Weekend Sale Limited Time 70% Discount Offer - Ends in 0d 00h 00m 00s - Coupon code: xmas50

ARM EN0-001 - ARM Accredited Engineer

ARM EN0-001 Premium Access     Download Demo    
Page: 4 / 7
Total 210 questions

Which of the following operations would count as intrusive to normal processor operation?

A.

Tracing using Embedded Trace Macrocell (ETM)

B.

Halt mode debugging

C.

Monitor mode debugging

D.

Using the Performance Monitor Unit

In a Cortex-A processor, assume an initial value of R1 =0x80004000.

If the following instruction causes a data abort, what value will R1 contain on entry to the abort handler?

LDR R0, [R1, #8]!

A.

0x80003FF8

B.

0x80004000

C.

0x80004008

D.

R1 contents are unpredictable

Which of the following is an optional extension to the ARMv7-A architecture?

A.

VFP

B.

The System Control Coprocessor (CP15)

C.

Support for memory barriers

D.

A Memory Protection Unit conforming to the PMSA

The following C function is compiled with hard floating point linkage.

float function(int a, float b, int c, float d);

Which register is used to pass argument c?

A.

R0

B.

R1

C.

R2

D.

R3

To return from a Data Abort handler and re-execute the aborting instruction, what value should be loaded to the PC?

A.

PC=LR

B.

PC=LR44

C.

PC=LR-4

D.

PC=LR-8

Which TWO of the following options can the ARM Compiler (armcc) directive__packed be used for? (Choose two)

A.

To tell the compiler to use only Thumb code

B.

To tell the compiler to produce code of minimum size

C.

To tell the compiler to use the v6 SIMD pack/unpack instructions

D.

To tell the compiler that an object can be on an unaligned address

E.

To tell the compiler not to perform padding inside structures

A simple method of measuring the performance of an application is to record the execution time using the clock on the wall or a wristwatch.

When is this method INAPPROPRIATE?

A.

When executing the software using a simulation model

B.

When the processor is a Cortex-R4

C.

When instruction tracing is enabled

D.

When the processor is not executing instructions from cache

The disassembly of a program written in C shows calls to the function__aeabi_fadd. Which one of these compiler floating point options could have been used?

A.

Hard floating-point linkage

B.

Soft floating-point linkage without floating-point hardware

C.

Hard floating-point linkage with optimization for space

D.

Soft floating-point linkage with floating-point hardware

When an ARMv7-A MPCore system is in SMP mode, which of the following TWO operations can the processor handle automatically? (Choose two)

A.

Coherency management between all L1 data caches

B.

Broadcast of some inner-shared cache and TLB maintenance operations

C.

Broadcast of some outer-shared cache and TLB maintenance operations

D.

Coherency management between all L1 instruction caches

E.

Coherency management between all external caches

Which of the following techniques can be used to obtain a precise count of clock cycles when profiling software over an arbitrarily long period of time using the Performance Monitoring Unit?

A.

A dedicated real-time clock to provide the total cycle count

B.

Use of the divide-by 64 counting option to avoid an overflow of the cycle counter

C.

Use of the overflow interrupts, to extend the range of the built-in 32-bit counter

D.

Modification of the application software being profiled, to insert timestamps at regular intervals