ARM EN0-001 - ARM Accredited Engineer
What is the maximum value of the immediate field in an ARM SVC instruction?
Implementing loops using a decrementing counter which exits the loop when a counter reaches zero can be beneficial for power and performance. This is because:
The effect of clicking the Stop button in a debugger is to:
When building code for both ARM and Thumb states, which tool decides for each function call whether to use a BL or BLX instruction?
Which of the following statements regarding Strongly-ordered memory is architecturally FALSE?
Which power mode describes the state where the ARM processor is powered down, but its Level 1 caches remain powered?
An external debugger would need to clean the contents of the processor data cache in which of the following cases?
In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)
What view in a debugger displays the order in which functions were called?
A Just-In-Time compiler writes instructions to a region of memory that is configured using a writeback cache strategy. For the locations that have been written, what is the MINIMUM cache maintenance that MUST be performed before the new instructions can be reliably executed?