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ARM EN0-001 - ARM Accredited Engineer

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Total 210 questions

What is the maximum value of the immediate field in an ARM SVC instruction?

A.

0x0

B.

0xF

C.

0xFF

D.

0xFFFFFF

Implementing loops using a decrementing counter which exits the loop when a counter reaches zero can be beneficial for power and performance. This is because:

A.

A simpler branch instruction can be used.

B.

Decrementing variables uses less power than incrementing them.

C.

The decrement and branch operations can be encoded as a single instruction.

D.

The loop termination condition check can be integrated into the subtract operation.

The effect of clicking the Stop button in a debugger is to:

A.

Put the processor(s) into debug state.

B.

Force the processor to execute a BKPT instruction

C.

Hold the processor in a Reset condition

D.

Re-initialize the memory contents.

When building code for both ARM and Thumb states, which tool decides for each function call whether to use a BL or BLX instruction?

A.

The linker

B.

The archiver

C.

The compiler

D.

The assembler

Which of the following statements regarding Strongly-ordered memory is architecturally FALSE?

A.

Address locations marked as Strongly-ordered memory are never held in a cache

B.

The architecture does not permit speculative data accesses to Strongly-ordered memory

C.

A write to Strongly-ordered memory is permitted to complete before it reaches the peripheral or memory component accessed by the write

D.

The number and size of accesses to Strongly-ordered memory must be the same as that specified by the program

Which power mode describes the state where the ARM processor is powered down, but its Level 1 caches remain powered?

A.

Run mode

B.

Dormant mode

C.

Standby mode

D.

Shutdown mode

An external debugger would need to clean the contents of the processor data cache in which of the following cases?

A.

When it changes the contents of ARM registers (r0-r15)

B.

When it displays the contents of an area of cacheable data

C.

When it displays the contents of an area of cacheable code

D.

When it sets a software breakpoint

In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)

A.

VA == PA; No address translations; instructions and data are not cached

B.

VA! = PA; No address translations; instructions may be cached but not data

C.

VA == PA; Address translations take place; data may be cached but not instructions

D.

VA == PA; No address translations; instructions may be cached but not data

What view in a debugger displays the order in which functions were called?

A.

The Call Stack view

B.

The Memory view

C.

The Registers view

D.

The Variables view

A Just-In-Time compiler writes instructions to a region of memory that is configured using a writeback cache strategy. For the locations that have been written, what is the MINIMUM cache maintenance that MUST be performed before the new instructions can be reliably executed?

A.

Instruction cache clean only

B.

Instruction cache invalidate only

C.

Data cache clean and instruction cache invalidate

D.

Data cache invalidate and instruction cache invalidate